Palmchip provides turnkey SoC & ASIC solution for its customers. Palmchip can develop the architectural details in conjunction with the customer’s requirements and implement the design in HDL. Palmchip also simulates and verifies the design and performs synthesis and timing closure. Our vast experience in IP and SoC framework development allows Palmchip to provide a unique set of services to its customers which other competitors might not be able to perform. Palmchip has used its experience to help clients turn out first time working silicon in mobile, consumer electronics, and storage domains.
Product Definition
- Specification development
- High level architecture modeling and analysis
- Logical Partitioning
- Mirco-Architecture definition
- Technology Selection
Implementation
Verification
- Model Development
- Test bench Development
- Code Coverage
- Random Testing
- RTL and Gate equivalency
Synthesis and Timing
- RTL synthesis
- Pre and Post Layout Timing closure
- Testability (Scan Insertion, JTAG, ATPG)
Foundry Interface
- Release design to foundry
Palmchip has vast experience in working with
- MIPS, ARM and Tensilica processors
- AMBA bus
- High Speed Memory Interfaces (such as DDR)
- Standard External Interface buses (PCI, USB)