CE-ATA is a standard for storage devices that is targeted for the embedded market. The low pin count and small form factor make it an ideal solution for the handheld applications area. The existing MMC specification is used as the electrical interface for CE-ATA.
Palmchip provides a highly programmable and feature rich CE-ATA host controller for its customers. The CE-ATA host controller provides both PIO and DMA mode for data transfer. The DMA controller can be used where high bandwidth and low CPU overhead is required. While designs that are targeted for low bandwidth areas can remove the DMA controller and just use PIO mode to satisfy their requirements, thus saving on gate count. The host controller also provides a proprietary clock speed controlling feature which can be used to control data transfer rates dynamically when a CPU is not in a position to service regular data transfer rates.
Features
MMC
- Compliant with Multimedia card specification Ver.4.1
- Supports 1, 4, 8 bit data width MMC
CEATA
- Compliant with CE-ATA specification Ver.1.1
- ATA reduced command set implemented
- Implements CMD60, CMD61 as specified in CE-ATA
- CE-ATA task file emulation
DMA
- Single channel DMA for transmitting and receiving data
- Descriptor and non-descriptor mode
- Pause, abort features implemented
CPU Interface
- Master interface for the DMA controller
- Target interface for programmable registers
- 32-bit data bus
- AHB or CoreFrame II
- Read/Write FIFO with programmable threshold
Clock Speed
- CPU interface runs up to 133MHZ in TSMC 0.18u
- MMC interface runs up to 52MHZ in TSMC 0.18u
Gate Count
- Approximately 45K in TSMC 0.18u (includes DMA controller and FIFO)