The DDR/DDR2 memory controller is composed of a single-ported memory controller core with an additional layer for multi-port applications through a CoreFrame-II CrosSwitch.
The core contains a PalmBus control interface and registers for configuration, control and status, a dedicated CPU interface optimized to minimize CPU latency, a scheduler that manages the memory requests received from the DMA devices, a memory control state machine core that controls the protocol to the DDR/DDR2 memories, and interface for the DDR/DDR2 memory data, data strobes and control signals.
Features
DDR/DDR2
- Supports 32 or 64-bit data bus
- Support for 4 or 8 data masks and strobes
- Fixed length burst of 4 is supported
- Supports 4-chip selects
- Supports 2GB of total memory address space
- Multiple page open management scheme
- Programmable timing parameters for
- CAS latency from 2-6 clocks (no half-clock latencies
- Row Activate
- Recovery after refresh
- Pre-charge
- Refresh period
- Self refresh mode per chip select
- Power down mode per chip select
- Mode-register set (MRS)
- Programmable MRS data values
- Preset initialization sequence available
Port Interfaces
- Dedicated CPU channel to minimize CPU latency
- Multiport concurrent channels for non-CPU masters
- Transaction scheduler for maximum performance
- 32-bit or 64-bit data bus
- CoreFrame II bus supported
- Separate 32-bit interface for programmable registers
Clock Speed
- CPU interface runs up to 200MHZ in 0.13u
- Multiport concurrent channels for non-CPU masters
- DDR interface runs up to 400MHZ in 0.13u