Hashing functions are extensively used in several applications, such as
- Digital Signatures
- Electronic Data Transfer Authentication
- On-line Banking and Electronic Fund Transfer
- Encrypted Data Storage
- IPSec
The hash core from Palmchip is a dedicated hardware accelerator that calculates the hashing function (or the message digest) for given byte oriented data or message, and one of the few cores in the market which comes with an integrated bus interface and DMA engine. The hash core supports both PIO and DMA mode of operations. The hash core implements the most widely used hashing algorithms SHA-1, SHA-256 and MD5 in a single core. The support for the multiple modes makes the hash engine particularly suitable for implementation of internet security protocols, such as IPSec that requires multiple authentication algorithms. The input data is padded according to the specific requirement of the hashing algorithm and endian-conversion is performed in the hardware.
Features
HASH Algorithms
- SHA-1, SHA-256 and MD5
- Fully compliant with FIPS 180-2 specifications and RFC1321 respectively
- The message pre-processing, data framing and endian conversion is performed dynamically by the core according to the specific requirement of the algorithm
DMA
- Full-Duplex 2-channel DMA for transmitting and receiving data
- Independent transmit and receive FIFO's
- Command Queue or Descriptor mode support
- Scatter-gather operations supported
- Memory to Memory data transfer supported
- Pause, abort features implemented
CPU Interface
- Master interface for the DMA controller
- Target interface for programmable registers
- Input data queue for PIO and DMA mode
- 32-bit data bus
- Palmchip CoreFrame II bus interface(AHB support available on request)
Clock Speed
Gate Count
- Approximately 80,000 in TSMC 0.18u