The BK-3754 SCCI (smart card communications interface) core is a specialized UART, designed to meet specific ISO/IEC 7816-3 protocol requirements. It interfaces to a controlling processor within the CoreFrame® architecture via the PalmBusTM interface. This core is a fully synchronous design and may be implemented with or without FIFO’s.
Features
- Even/odd parity or no parity generation and detection
- Programmable one or two stop bits per character
- Asynchronous half and full duplex modes
- Auto switching between Transmit and Receive modes
- Error auto-detect and auto-retry
- 3 maskable interrupts
- Programmable Baud rate clock
- Transmit and Receive FIFOs
- Configurable receive and transmit buffer interrupts
- Data format supported: 1 start bit, 8 data bits, optional parity bit, 1 or 2 stop bits
- False start bit detection
- Loop back and set break diagnostic modes
- CoreFrame® SOC integration architecture