In any processor-driven design, a number of peripheral devices are needed. These include timers, DMA engines, interrupt controllers and memory controllers. In many cost-sensitive applications, a shared memory structure is utilized to reduce memory component costs. An architecture is needed which addresses the memory needs of all devices without severely degrading the performance of any single device.
The CoreFrame® architecture was developed to fill the need for applications to be developed quickly and be portable between foundries. Synthesis fills this requirement; however an architecture is needed that is synthesis friendly for quick development without sacrificing performance.
AcurX51 Configurable SoC Platform AcurX Lite Configurable Soc Platform AcurX Configurable SoC Platform