The 80251 core executes the instruction in a single clock cycle, and is an instruction set compatible implementation of the MCS-251 family. It’s about 3.19 times faster on average then the MCS-251 family. The Dhrystone v2.1 benchmark score is 0.258 DMIPS/MHz. The PALM80251 has a total addressable memory of 16Mbytes of which 16Kbytes is implemented as on–chip program memory, 1KBytes of on-chip data RAM, and the rest as external memory which can be used as RAM or ROM.

The PALM80251 can be used to implement a HAN coordinator and gateway device to communicate between the numerous devices which might be running inside a home or office building, and the internet gateway to enable remote energy management, where home or business appliances could be controlled from smart phones or PC to save energy.

• Single Clock Cycle Instruction Execution
• 16KBytes of On-chip Program Memory
• 1024 bytes of On-chip Data RAM
• Up to 64Kbytes of external Program Memory
• Up to 16Mbytes of external Data Memory reserve for ROM/RAM
• Enhanced architecture for performance improvements
• Wait state support for slow external peripherals
• Standard 2 16-bit timers/counters
• 6 Source/5 Vector interrupt structure with two priority levels.
• No multiplexed I/O ports
• 31 General purpose I/O Ports
• Full Duplex Serial Port